The present invention relates generally to a system and method for adjustment of clock signals in multi-input CMOS image sensor processor systems (also referred to as “CIS image systems” or “CIS image processor systems”), and more particularly to an architecture which provides an integrated circuit including multiple parallel CIS (CMOS image sensor) modules that require only a single analog to digital converter (ADC), in order to increase system imaging speed, reduce power consumption, and avoid analog-to-digital conversion inaccuracies due to externally generated noise.
The CMOS image sensor samples the photons of the incoming light, and its resulting charge is converted to a voltage which subsequently is coupled to a the input of a corresponding sample/hold amplifier, which has an associated settling time. A typical CMOS image sensor (also referred to simply as a “CMOS sensor”) operates to accumulate photons and generate corresponding charge representative of the light intensity during the present time interval, and at the same time charge previously generated (during the previous time interval) is being stored and presented as an output voltage to be sampled. The sampled voltage ordinarily is steered and amplified to provide an analog output signal which typically is converted to a digital output signal. Some CMOS sensors have the capability of having their output signals enabled or strobed in, response to rising edges of an enable or strobe signal. Other CMOS sensors have the capability of having their output signals enabled or strobed in response to falling edges of the enable or strobe signal, and yet other CMOS sensors are programmable to provide either capability. CMOS sensors have associated output signal settling times during which sampling capacitors are being charged by the CMOS sensors.
FIGS. 1A-1C are believed to be indicative of the closest prior art, which includes multiple CIS signal sampling and conversion circuits arranged to receive analog inputs from corresponding CMOS sensors and convert them to corresponding digital output signals. Such systems are commonly used in various applications, for example in copy machines that include multiple CIS channels clocked by an external clock generating system. The external clock generating system routes a single clock signal into different CIS sampling and conversion circuits. For example, multiple CMOS sensors and associated lens systems are commonly used on a moving sensor light bar of a copier for scanning a face of a document. In some cases, there is a second sensor light bar for essentially simultaneously scanning the other face of the document. In the past, the CMOS sensors of such systems have been operated in a serial fashion, wherein serial sampling and analog-to-digital conversion of a CMOS sensor output voltage are performed using corresponding dedicated sampling circuitry and a dedicated ADC for each CMOS sensor. The settling of the sample/hold circuits in the prior art have been problematic.
CMOS sensors usually have two outputs. One is the signal level SIG, and the other is a reset output RST. The reset output RST functions as the reference voltage level for the CMOS sensor. In FIG. 1A, CIS image processing system 1 includes first and second “banks” of CMOS sensors. The first bank includes 4 CMOS sensors 14A(1-4) which produce output signals SIG1-4 and reset signals RST1-4. The signals SIG1-4 are selectively switched by switching circuit 18A into a first sample/hold circuit 43-1, and the signals RST1-4 are selectively switched by switching circuit 18B into first sample/hold circuit 43-1. Similarly, the second bank includes 4 CMOS sensors 14A(5-8) which produce output signals SIG5-8 and reset signals RST5-8. The signals SIG5-8 are selectively switched by switching circuit 18C into a second sample/hold circuit 43-2, and the signals RST5-8 are selectively switched by switching circuit 18D into second sample/hold circuit 43-2. The outputs of sample/hold circuits 43-1 and 43-2 are connected to inputs of first and second ADCs (analog to digital converters) 45-1 and 45-2, respectively. Control circuit 47 receives a clock signal ADC CLOCK and a control signal CONTROL BIT, for the purpose of controlling the way ADC CLOCK is directed to sample/hold circuits 43-1,2 and to ADCs 45-1,2.
For example, depending on the state of CONTROL BIT, sample/hold circuits 43-1 and 43-2 can sample the CMOS sensors 1-4 and 5-8 in phase or out of phase with each other, and accordingly, ADCs 45-1 and 45-2 can operate either in phase or out of phase with each other. In either case, the amount of time available for sampling of the CMOS sensor outputs is one-half of the cycle time of ADC CLOCK.
Referring to FIG. 1B, the waveforms of the signal sample clock SIG SAMPLE CLOCK, and the reset sample clock RST SAMPLE CLOCK, the main signal SIG, and the reset signal RST of a CMOS sensor are shown. The voltage level of RST is sampled every RST SAMPLE CLOCK pulse 2 and the voltage level of SIG is sampled every SIG SAMPLE CLOCK pulse 3, typically to accomplish correlated double sampling. A single sampling capacitor (e.g., see capacitors C1-8 in FIG. 1C) samples the voltage level of RST pulse 2 during a first half cycle of ADC CLOCK, and the sensor output signal SIG then is sampled on the next half-cycle of ADC CLOCK. The feature “A” in the SIG waveform illustrates a perturbation that occurs when the sampling capacitor has some residual charge remaining from the previous conversion. Only one half of a clock cycle of ADC CLOCK is available for the perturbation “A” to settle out. That amount of settling time is indicated by arrows 5 between the perturbation “A” and the sampling time indicated by vertical dashed line 4. That condition requires that the output buffer or amplifier (not shown) of the CMOS sensor settle rapidly. That in turn may cause analog to digital conversion inaccuracies. (In some cases, costly, power-consuming external buffers/amplifiers need to be connected to the outputs of CMOS sensors in order to achieve more rapid settling.)
FIG. 1C illustrates an implementation in which outputs of 8 CMOS sensors are switched into 8 corresponding sampling capacitors C1-8, all in response to the same sampling signal CLKS which are shown in the timing diagram of FIG. 1D. Each sampling pulse of CLKS has a relatively short duration, equal to that of ADC CLOCK, for a duration equal to one half of the ADC CLOCK cycle. (In the prior art, there also are similar image processing systems that have two different sampling phases, for example, to sample 4 CMOS sensors during one phase and 4 other CMOS sensors during the next phase. The prior art systems referred to have utilized two ADCs, as shown in FIG. 1A. However, these systems also have the shortcoming that each CLKS clock pulse has the same relatively short duration equal to half of the ADC CLOCK cycle time.)
A problem of the prior art systems is that there cost is higher than desirable because more than one costly sample/hold circuits and ADCs are required. Also, the prior art results in less accuracy of the digital output signals than is desired because externally generated circuit board noise is coupled to and superimposed on the analog input signals received by the inputs of the ADCs, which results in analog to digital conversion inaccuracies due to the fact that sampling timing is fixed. Furthermore, if more than one A/D or S/H is used, then the gain circuitry and DAC circuitry of each channel has a net mismatch associated with it relative to the other channels consisting of both systematic and random effects not limited to gain mismatch and offset mismatch.
In the past, attempts have been made to operate the sample/hold amplifier at the same speed as the ADC coupled to the output of the sample/hold amplifier. However, this approach has been problematic because high speed operation usually requires correspondingly large amounts of power consumption, and also because it has typically been necessary to use costly external amplifier/buffers.
An externally generated clock signal applied as an input to an integrated circuit frequently is susceptible to outside noise influences that require clock signals be low pass filtered to reduce square wave harmonics. Once the “rounded” low-pass-filtered clock signal reaches the CIS integrated circuit chip, the clock signal must be “squared” again for use within the digital image processing portion of the CIS integrated circuit chip. This introduces delays and clock timing errors that interfere with the timing of the CIS relative to the ADCs within the multi-input CIS image processor integrated circuit chip. Also, the time of occurrence of a rising edge of the CIS clock signal within the multi-input CIS image processor integrated circuit chip may be substantially different than the time of occurrence of the falling edge thereof. With inflexible timing, inaccurate analog to digital conversion often occurs, which limits the performance of the entire imaging system.
Thus, there is an unmet need for an improved system and method for providing multi-input CIS image processing integrated circuits that provide substantially increased imaging speed by, in effect, allowing parallel sampling of multiple CMOS image sensors and which also provide substantially reduced power consumption by allowing analog output signals produced by multiple CMOS image sensors to be coupled to the same input of a single ADC.
There also is an unmet need for an improved system and method for providing multi-input CIS image processing integrated circuits which avoid the difficulties of inaccurate analog to digital conversion due to coupling of noise present in a printed circuit board to the input of an ADC.